Pipelined Architecture Design of H.264/AVC CABAC Real-Time Decoding

This paper proposes a high performance 4-stage pipelined VLSI architecture of H.264/AVC CABAC decoder based on four sequential memory accesses. Through adoption of several speeding techniques such as redundant circuit and forwarding to eliminate the pipeline hazards, the parallelism among the interrelated decoding process has been fully exploited and the pipeline stalls are avoided. Additionally, by exploring parallelism in bypass mode, the proposed design decodes two successive bins in each cycle. Experimental result shows that the proposed architecture can achieve the throughput of more than 1 bin/cycle which meets the real time decoding requirement of HD1080i (1920x1088) video.