Improvement of TANOS NAND Flash Performance by the Optimization of a Sealing Layer

We presented an optimization of an interfacial SiO
₂
sealing layer between the nitride and top dielectric of a TANOS stack showing a strong retention improvement thanks to an increased DeltaEc to Si
₃
N
₄
, that prevents vertical escape of the electrons through the top dielectric. In case of HfAlO top dielectric, it also provides a better program/disturb margin.