An FPGA implementation Of 2-D CNN gabor-type filter

A field programmable gate array (FPGA) implementation of the Gabor-type filter is presented. The implementation uses the forward Euler approximation with optimal step size to solve the CNN cell-state equation. The FPGA is implemented on Xilinx Spartan XC3S400 device using 219 slices. An image of dimension 60 times 60 can be processed without using any external RAM only with the block RAM.