A Novel Approach for Multiplication over GF(2m) in Polynomial Basis Representation

In this paper a new approach for multipliers over GF(2
^m
) in polynomial (standard) basis representation is proposed. The proposed multiplier is a new construction for hybrid multipliers. The main advantage of this multiplier compare to other proposed multipliers is in the reduction unit which occupies less area on chip to implement. In this effect, first a new algorithm is presented, which computes the multiplication in n iterations. Using this algorithm, a new architecture is proposed. Then the proposed multiplier is analyzed in terms of gates complexity and gate delay. Implementation results of the multiplier over FPGA are also presented.