An All-Digital On-Chip Process-Control Monitor for Process-Variability Measurements

Process variability has become a major challenge in nanometer technologies. The trend is driven by Moore’s law, low-power requirements (i.e., low VDD), and shrinking device geometries. Understanding process variability is therefore a key to designing successful low-power multi-million gate SoCs. An all-digital onchip process control-monitor (PCM) that measures process variability is described. It is implemented in a 65nm dual-oxide triple- Vt bulk CMOS process and it measures 0.41mm2 [1]. Unlike traditional methods that measure standard device properties using analog or digital techniques [2,3], this PCM measures process variability in a way that is directly relevant to VLSI designers. Using simple statistics the measurements translate directly into electrical design rules. The monitor consists of 4 modules: 1) an array racer module to measure timing races caused by local mismatch, 2) a distributed jitter module to measure supply-induced jitter on an inverter chain, 3) a leaker module to measure keeper ratios for dynamic circuits, and 4) a distributed ring oscillator module to measure across-die process variability. The all-digital nature of the PCM reduces test time and cost and allows data collection in wafer or package form.