A 100nm Double-Stacked 500MHz 72Mb Separate-I/O Synchronous SRAM with Automatic Cell-Bias Scheme and Adaptive Block Redundancy

As multi-core processors become mainstream, the demand for high-density cache memories has increased. Conventional 6T-cellbased SRAMs do not provide enough density for this trend, although they do have the desirable feature of high-speed access. To overcome the density limitation, an SRAM using a doublestacked S3 (stacked single-crystal Si) SRAM cell was introduced for mobile applications [1]. This work demonstrates a high-speed SRAM using double-stacked-cell. From the process point of view, our design uses fully proven technologies for mass production at the sacrifice of cell size, from 25F2 to 36F2 [2]. In addition, peripheral only CoSix layers and a tungsten shunt wordline scheme are used for high-speed operation. From a circuit-design perspective, three schemes are introduced. They are automatic cell bias (ACB) for managing the current of SRAM cell transistors by controlling cell bias, adaptive block redundancy (ABR) for dealing with various defects from the new cell technology, and wordline pulse-width regulation (WPR) for adjusting wordline pulse-width according to cycle time.