Reliability analysis of copper interconnection in system-in-package structure

The system-in-package (SiP) is one of the popular designs to meet the trend of Integrated Circuit (IC) development. It is known for its small size, light weight, and multiple functionality. In this paper, a radio frequency front end module (RF-FEM) incorporated with the novel wafer-level chip scale package (WLCSP) technology is investigated. Generally the solder joints in WLCSP are the weakest portions due to the CTE mismatch between the PCB board and the package. For the SiP structure investigated, the filler polymer is treated as a good stress buffer layer to relax most CTE-mismatch-induced thermal stress. However, the interconnection laminated within the filler polymer is pulled by the expansion of the polymer with relatively higher thermal stresses. The reliability of copper interconnection between chips then becomes a serious issue for the SiP structure.