An acoustic echo canceler

The authors describe an experimental 1000-tap single-chip adaptive AEC (acoustic echo canceler) occupying 28 mm/sup 2/ of die area in 3- mu m, double-metal, p-well, CMOS technology. A floating-point format and power-of-two multiplications are chosen to simplify the hardware. To exploit pipelining and parallelism, interleaved data storage and multibank memory sharing the same addresses are designed. Hardware minimization is considered from both the system and the architecture perspective. In a loudspeaker telephone application, 27 dB of echo reduction is achieved after 1 s of convergence time.<
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