A 200-MHz CMOS phase-locked loop with dual phase detectors

A high-frequency integrated CMOS phase-locked loop (PLL) including two phase detectors is presented. The design integrates a voltage-controlled oscillator, a multiplying phase detector, a phase-frequency detector, and associated circuitry on a single die. The loop filter is external for flexibility and can be a simple passive circuit. A 2- mu m CMOS p-well process was used to fabricate the circuit. The loop can lock on input frequencies in excess of 200 MHz with either or both detectors and consumes 500 mW from a single 5-V supply. The oscillator is a ring of three inverting amplifiers and draws from an internal supply voltage regulated by an on-chip bandgap reference. This combination serves to reduce the supply and temperature sensitivity is less than 5%/V, and the oscillator temperature variation is 2.2% in the range of 25 to 80 degrees C. The typical oscillator tuning range is 112 to 209 MHz. The multiplying phase detector and phase-frequency detector exhibit input-referred phase offsets of <4 degrees and -24 degrees , respectively. A numerical system simulation program was written to explore the time-domain behavior of an idealized model based on the PLL design.<
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