Independent-Gate and Tied-Gate FinFET SRAM Circuits: Design Guidelines for Reduced Area and Enhanced Stability

Data stability of Static Random Access Memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also an important source of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. Two six transistor SRAM cells based on independent-gate FinFET technology (IG-FinFET) are described in this paper for simultaneously reducing the active and standby mode power consumption while enhancing the data stability and the integration density. With the first independent-gate FinFET SRAM cell, one gate of each double-gate access and pull-up transistor is permanently disabled in order to enhance the data stability while achieving write-ability with minimum sized transistors. With the second independent-gate FinFET SRAM cell, the threshold voltages of the access transistors are dynamically adjusted during circuit operation in order to maximize the memory integration density without sacrificing the performance and stability. The read stability is enhanced by up to 92% with the IG-FinFET SRAM cells as compared to a tied-gate FinFET SRAM cell with the same size transistors in a 32nm FinFET technology. Furthermore, with the IG-FinFET SRAM cells, the idle mode leakage power and the cell area are reduced by up to 36% and 11%, respectively, as compared to a standard tied-gate FinFET SRAM cell sized for comparable read stability in a 32nm FinFET technology.