Design and Implementation of area optimized AES algorithm on reconfigurable FPGA

Cryptography algorithms are becoming more necessary to ensure secure data transmission, which can be used in several applications. In this paper the hardware implementation of optimized area for the block cipher advanced encryption standard (AES-128) is introduced using field programmable gate array (FPGA). The core includes the key schedule expansion and storage, the encryption, the decryption, and 8-bit input/output data interfaces with full control. The design is based on optimized area by using the time sharing of certain resources and iteration architecture. The sub round key is obtained by 10 times iteration a round the optimized single key schedule module which designed by one S-box ROM and one inverse mix column. Also the cryptography data is obtained by 10 times iteration a round the optimized single round module which designed by two S-box ROM and two mix column for encryption and decryption mode. This is done by design optimized logic circuit, timing control blocks, and state machine. The proposed architecture was implemented by VHDL, schematic and core generator – based design which are synthesized, place and routed in Spartan3 chip XC3s400-5 using ISE web pack version 7 .1.04 with optimized area (2,699) slices and (≈10) Mbps throughput with (15264) ns latency and (45) MHz clock speed.