Reconfigurable computer application design considerations

The notion of a reconfigurable computer (RC) is nearly 50 years old. However, practical RCs, which were made possible by the advent of large capacity field programmable gate arrays (FPGAs), have only been available for about a decade and have been primarily used for integer and fixed-point applications. The jury is still out on whether RCs will become part of mainstream high performance computing. One of the primary roadblocks is the relative difficulty of mapping floating-point scientific applications onto reconfigurable platforms. This paper deals with some important high performance reconfigurable computer application design considerations. In particular, it takes a detailed look at “the three p’s,” which addresses the crucial relationship among performance, pipelining, and parallelism. It also expands upon “the FPGA design boundary,” which addresses some of the heuristics that allow developers to determine which application modules can be mapped onto the FPGAs. Finally, it looks at some of the RC design observations made by other researchers. By way of a few simple examples, these ideas are illustrated and then tied back to some recent research efforts to speedup applications using RCs.