A 1 GHz decimation filter for Sigma-Delta ADC

This paper presents the implementation of a high-speed decimation filter operating at Giga Hertz that is suitable for high-speed Delta-Sigma analog-to-digital converters. The filter is realized in a non-recursive architecture using a novel full adder and D flip-flop. The filter has been implemented in a 0.18μm/ 1.8 V CMOS technology for a decimation factor of 4. The operation frequency is 1 GHz and the power consumption of I and Q filters are 6 mW and 4 mW, respectively.