A low-leakage current power 180-nm CMOS SRAM

A low leakage power, 180-nm 1K-b SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly-developed leakage current reduction circuit called a “Self-controllable Voltage Level (SVL)” circuit was only 3.7nW, which is 5.4% that of an equivalent conventional memory-cell array at a V
DD
of 1.8V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area.