A Comparison of HCMOS-III and HMOS-III Technologies for 64K or Larger Static RAMS

A fundamental difference in the performance capabilities of HCMOS-III and HMOS-III technologies as applied to 64K or larger static RAMs has become apparent. These differences relate to the basic parameters of the transistors in the two technologies and the circuit configurations they appear in. Spacing considerations for tub margins or prevention of latchup do not influence the technology choice, since the area penalty for tub spacing is acceptable and epi substrates with careful layout reduce the latchup problem to a minimal level. This paper discusses the performance of these technologies using the same lithography and etching processes as applied to static RAMs in the 1.5um design rule range. It will be shown that a clear advantage in overall performance exists for the 1.5 μm HCMOS design and that previous design rule, current drive, and technology complexity advantages of the HMOS design do not exist at present.