Reduced Process Sensitivity of Polysilicon Emitter Contacts for VLSI Bipolar Transistors

Polysilicon emitter contacts play an increasingly important role in high-speed npn bipolar transistors, particularly for emitter thicknesses of 0.1 μm or less. When optimizing these contacts, both the emitter resistance and the base current must be considered[1,2]. These two parameters are strongly dependent on the morphology of an interfacial layer between the poly and the single-crystal silicon. For high-speed applications, high polysilicon doping levels and moderate to high anneal temperatures are preferred in order to reduce the emitter resistance by partially breaking up the interfacial oxide[1,2]. The integrity of the interfacial oxide and the extent of partial epitaxial alignment of the polysilicon are very sensitive to the process, leading to large variations in base current and emitter resistance from run to run[1]. This paper discusses a characterization of two methods of reducing this process sensitivity: rapid thermal annealing (RTA) to induce epitaxial alignment with the substrate, and replacement of the interfacial oxide by an extremely thin thermal nitride layer.