High Density Fetmos Eeprom Cell Using ONO Inter-Polysilicon Dielectrics

There are many floating-gate EEPROM cells (1-5),that use Fowler-Nordheim tunneling through thin dielectrics for program and erase operation. All these cells contain three common basic elements: a select transistor, a floating-gate transistor and a tunneling area. Attempts to reduce EEPROM cell size are by merging or integrating some of the basic elements in a cell's structure. A reduction in cell size is achieved by integrating the tunnel area into the drain diffusion region of the floating-gate transistor (3,5) as for a FLOTOX cell in Figure la. Further reduction in cell size is achieved by total merging of the tunnel area into the floating-gate transistor, as for the FETMOS ( Floating-gate Electron Tunneling MOS) cell (2) in Figure 1b.