Response Surface Methodology for statistical characterization of nano CMOS devices and circuits

The accurate prediction of the impact of process variations on circuit performance is very crucial in deciding the parametric yield of integrated circuits. This paper presents the simulation methodology for studying the impact of process variations on device and circuit performance in nanometer regime. In this paper, an empirical model for power and delay of 45 nm node CMOS inverter is build using the well-known response surface methodology. This work also compares the suitability of different response design in terms of model accuracy.