A Study of Chip Top Delamination in Plastic Encapsulated Packages under Temperature Loading

This work is focused on numerical investigation of the corner delamination behavior at the chip top surface of plastic encapsulated semiconductor packages which is induced under temperature loading. Two points of interest are pursued in this study: 1) impact of mold compound (MC) material properties and 2) influence of package geometry on the delamination behavior. For the first part we identify influence of Young's modulus and coefficient of thermal expansion (CTE) on the fracture mechanics parameters of the interface crack by comparing two highly glass filled epoxy MCs typically used by the semiconductor industry. The second part is concerned with the influence of the chip and mold cap thickness on the crack behavior at the chip / MC interface. Since mitigation of delamination propagation inside the package is the primary goal in package development, the work is concentrated on the analysis of small (undetectable) initial delamination using a 3D finite element analysis. Results of the current work give ways for reducing risk of chip top delamination.