The 1st Level & 2nd Level Solder Joint Reliability Co-design for Larger Die Flip Chip Package

This work focuses on co-design of the 1
^st
level and 2
^nd
level solder joint reliability analysis of a flip chip package, with large die. Model with all the layered structures for the build up substrate is compared with the compact model of equivalent substrate. Two 1
^st
level solder bumps are modeled along with the 2
^nd
level solder balls. The fatigue life of 2
^nd
level solder joint is estimated by the Darveaux's method. Inelastic strain energy density per cycle accumulated in the solder bumps during thermal cycling is used to predict the trend of fatigue life for the 1
^st
level bumps. Model with and without heat spreader are considered in this study. Then a series of parametric study is performed by varying different crucial package dimensions which play an important role in solder fatigue life. Effects of die thickness, substrate thickness and heat spreader type on solder fatigue life are analyzed in this paper.