A 6ps resolution pulse shrinking Time-to-Digital Converter as phase detector in multi-mode transceiver

This paper presents a new phase detector in an all digital phase locked loop which converts the phase difference between one reference clock edge and one divided oscillator edge into a digital word. This digital word can be converted into a digital representation of the actual phase error which can be utilized in an all digital phase locked loop. 6 ps resolution for this Time-to-Digital Converter (TDC) is realized in a standard 0.13 μm CMOS technology. Its Full-Scale-Range (FSR) is 4500 ps.