Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures

Network-on-chip (NoC) architectures provide a high-performance communication infrastructure for system-on-chip designs. Circuit-switched networks guarantee transmission latency and throughput, and hence are suitable for NoC architectures with real-time traffic. In this paper, we propose an efficient integrated scheme which automatically maps application tasks onto NoC tiles, establishes communication paths, and allocates a proper bandwidth for each communication path. Simulation results show that our design provides an effective solution for a critical step in the NoC design. The cost and latency of the switch in the circuit-switched network can be lowered down with our scheme.