FPGA Implementation of an Efficient 3D-WT Temporal Decomposition Algorithm for Video Compression

In this paper, the hardware design and FPGA implementation of a new efficient three-dimensional wavelet transform (3D-WT) algorithm for video compression is presented. This algorithm performs the temporal decomposition of a video sequence in a more efficient way than the classical 3D-WT algorithm. It exhibits lower memory demands and lower latencies for the compression and decompression processes than the classical one. This makes the addressed algorithm fits better for real-time video processing. The hardware design is based on the use of the transposed-form FIR filter structure which is hereby compared to the direct-form FIR filter. The former is found to exhibit less clock latency and less chip area utilization. The reference design is made scalable to any wavelet filter coefficients and to fit for any frame size. The chip area utilization is compared upon the FPGA implementation at different frame sizes. The designed system can be used for real-time video applications.