Tag compression for low power in instruction caches

As power consumption of the cache memory in modern processor designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing instruction cache power based on the operation of the Tag Compression Registers added in the cache system. The power savings show that, when the size of the Tag Compression Registers is properly fixed, the average saving on the power consumption of the instruction cache could be up to 64% compared with the traditional instruction cache structure.