Design-for-Manufacture for Multigate Oxide CMOS Process

Design-for-manufacture (DFM) for thick gate oxide layout in a dual gate oxide product is investigated. Careless placement and layout for thick gate oxide transistors in the multigate oxide chip can cause significant yield loss. The root cause of the yield loss is that the thick gate oxide can impact the uniformity of the adjacent thin gate oxide thickness. Further experiments' results show that the optimization of thick gate oxide transistor layout for the same product can improve the yield. Besides tweaking the gate oxide etching process to overcome the difficulty of multi oxide product manufacture, the guidelines for a good gate oxide layout practice are provided to facilitate the manufacture.