A Fully Integrated 48-GHz Low-Noise PLL with a Constant Loop Bandwidth

We present a dual-loop PLL architecture for low-noise frequency synthesizers. The approach is experimentally verified for a 48 GHz PLL in 0.25 mum SiGe BiCMOS technology intended for a 60 GHz wireless transceiver. The design employs two parallel charge pumps one of which dominates the loop dynamics and is biased at optimum output voltage. This equalizes the loop bandwidth and reduces charge pump mismatch.