Improved power scaling issue for pipeline ADC

In this paper an improved method to design a power optimized pipeline ADC is presented. By analyzing the architecture of SHA and the dependency of power on SNR, supply voltage and sampling rate, the flowchart instructing the design of pipeline ADC is put forward which simultaneously determines the resolution distribution, the optimum value for capacitors scaling factor, the parameter of OTA in each stage. A 0.18-mum 10-bit 80-MS/s CMOS prototype achieves 58.1 dB SNDR is implemented to validate the power scaling approach.