Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GPS/Galileo Low-If Receiver

In this paper, starting from theoretical considerations on the chosen architecture, chip design and measurement results are presented for a continuous-time quadrature bandpass sigma-delta (ΣΔ) modulator for a combined GPS and Galileo Low-IF receiver. The modulator chip was designed in a standard 0.25μm CMOS technology. The designed CT quadrature bandpass ΣΔ modulator has a power consumption of 20.5 mW with 1.8-V supply voltage, a dynamic range of 57.5 dB and 50.2 dB and a peak SNDR of 52.9 dB and 48.4 dB for GPS/Galileo, respectively. The core area of the chip is 0.37 × 0.54 mm
²
.