New Conditional Sampling Sense-Amplifier-Based Flip-Flop for High-Performance and Low-Power Application

In this paper a new sense-amplifier based flip-flop is proposed for high-performance and low power application. The proposed new design employs conditional techniques to create conditional sampling windows to eliminate redundant internal transitions. The proposed single edge-triggered D flip-flop is based on charted semiconductor 0.18-mum CMOS process. The proposed design shows a great reduction in power dissipation especially at lower data activity rate, with 50% reduction at 50% data activity and 25% less power at 25% data activity. The proposed new design obtained a reduction of 21% for its data-to-output delay and an overall improvement of 30% in the power-delay-product (PDP) when compared to the recently published low-power high performance differential conditional data mapping flip-flops. It also has lesser transistor count.