An FFT-based jitter separation method for high-frequency jitter testing with a 10x reduction in test time

This paper proposes an FFT-based method that separates random jitter from deterministic jitter in clock and data patterns, with a 10X reduction in test time. The method has been verified experimentally on a 2.5 Gbps clock pattern & 7-stage PRBS, and gives results that are comparable to existing methods.