An FPGA-Based Architecture for ECC Point Multiplication

In this paper, we present a low area design for the elliptic curve point multiplication over GF(2
^m
), which is developed for FPGAs implementations. The design is implemented for a 193-bit field size. Our FPGA implementation targets a Xilinx VirtexS device. The design has been synthesized using Precisionreg (RTL Synthesis tool), applying Xilinx special mapping and optimization algorithms within Precision to produce good area results. Implementations have proven to be efficient in area cost compared to the published FPGA-based for elliptic curve cryptography designs. The design is approximately 43% smaller than the most recent published designs.