A 35mW 12 bits 25 MS/s pipelined analog to digital converter

The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with the analog to digital converter. We present here a 12 bits 25 MHz analog to digital converter using the pipe line architecture. Its’ first stage is a charge redistribution sample and hold, then follow ten 1.5 bit sub-ADC and finally a 2 bit flash. A CMOS 0.35μ process is used, and the dynamic range covered is 2V. The analog part of the converter can be quickly switched (a couple of ps) to a standby mode that reduces the DC power dissipation by a ratio of 1/1000. The size of the converter’s layout including the digital correction stage is only 1.7mm*0.6mm, and the total do power dissipation is 35mW.