A CCD clock controller ASIC using novel design techniques integrated in a CMOS 0.8μm SOI high voltage process

An ASIC designed to provide the clock signals to the focal plane CCDs for the SNAP satellite project is presented. A prototype has been implemented in a CMOS 0.8μm SOI high voltage process in order to accommodate a 20V output swing. The circuit consists of a main charge pump multiplying the 4V power supply voltage +/−16V followed by a controlled current source setting the clock voltage plateaus. A bridge of switches provides the clock voltage transitions at the output. This circuit is designed to operate at room temperature for test purpose and at 140 K, which will be the operating temperature. Novel design techniques used in this chip will be presented in detail along with measurement results obtained on the prototypes.