High Speed Interface Wirebond Modeling Division Methodology

As the frequency of the high speed interfaces in computer platforms and systems continue to ramp due to architectural advancement and strong market demands, electronic packages have been stretched to its limit to support these interfaces. The increase in the complexities caused the electrical modeling methodologies to become increasingly complicated and tedious too. New modeling methodologies have to be developed to shorten through put time without sacrificing much of its accuracy. Wirebond package has been in the industry for a long time due to its good performance and relatively low cost compared to Flip Chip package. Even though facing huge challenge to support higher frequency interfaces, wirebond package still proves to be a capable and cost effective solution, but at the expense of requiring extensive and tedious modeling work. This paper discusses the high speed interfaces wirebond modeling methodology proposed to improve through put time and scalability besides reducing multiple models extraction required and human errors associated with it. This is done by mathematically dividing the parasitic Resistance, Inductance and Capacitance obtained from a full wirebond model by the number of segments required based on the interface frequency. In order to obtain a 3-Dimensional package electrical model, the wirebond models are extracted and analyzed based on their actual physical dimension from a specific package for accurate results using AnsoftLink™ and Ansoft Q3D Extractor®.