DLX gold: design and implementation of a DLX microprocessor with single precision floating- point operations

Floating point (FP) arithmetic is an integral part of modern processors because numerous programs need to perform FP operations. The project aimed to implement a 32-bit pipelined DLX microprocessor that can handle single precision FP operations. This project made use of the class 1 architecture for FP operations, which has an independent unit for addition, multiplication, and division. Furthermore, dynamic scheduling, specifically the speculative Tomasulo algorithm, was employed to effectively handle the parallel execution of instructions. The structural model was implemented using VHDL (VHSIC hardware description language). Afterwards, the functionality was verified using the Cadencereg design system software. Finally, the schematic and layout were produced also using Cadencereg. The implemented microprocessor was then characterized in terms of speed, area, and power consumption. The addition of the FP Units resulted in a 53% decrease in execution time, with an area and power overheads of 98% and 65% respectively.