An all-digital reused-SAR delay-locked loop with adjustable duty cycle

An all-digital delay-locked loop (DLL) with multiple outputs and adjustable duty cycle is presented by using the reused successive approximation register (SAR). This DLL provides the multiple synchronous clocks with independently adjustable duty cycles. The proposed reused SAR is similar to a conventional SAR, but it saves a lot of area. The clock duty cycle is adjusted by a 5-bit coarse code and a 2-bit fine code shared each other. This DLL has been fabricated in a CMOS 0.18 mum technology. The measured input frequency is from 300 MHz to 800 MHz. The measured peak-to-peak jitter is 9.78 ps at 800 MHz. The power consumption of this DLL with one output clock is 2.7 mW at 800 MHz. The maximum duty cycle variation at 300 MHz is less than 1%. The area of this DLL is 0.054 mm
²
.