Time dependence of bias-stress induced threshold-voltage instability measurements

Silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are very attractive devices for high temperature, high frequency, and high power applications, allowing voltage controlled transistor operation with limited cooling requirements. However, interfacial charge (interface traps, oxide traps, and fixed charge) at and near the SiC-SiO
₂
inversion channel-gate insulator interface can lead to degradation in device performance by reducing the effective channel mobility and shifting the threshold voltage. The threshold voltage instability measurement is a method of determining a lower bound for the number of oxide traps present. Finally, a shift of 1 V could cause a dramatic increase in the subthreshold current, leading to a dramatic increase in drain leakage in the off state if the threshold voltage is not positive enough.