Temperature dependent empirical modeling of proximity diffused Si esaki diodes and memory circuits

In this paper, the modified Sze model developed by the authors fits the measured IV characteristics very well for both forward and reverse biases at temperatures ranging from 23degC up to 200degC. Simulations of a TSRAM timing diagrams at multiple temperatures show the viability of using the developed model for accurate simulation and characterization of tunnel diode augmented CMOS circuits, including temperature effects.