Predictive technology modeling for 32nm low power design

In this paper, a new version of PTM down to 32nm node for low power design has been developed. Predictive Technology Model (PTM) for nanoscale CMOS was first developed in 2000. It was widely used in early stage design exploration, providing key insights into advanced process and design research. PTM for high performance design was further improved to achieve a more physical prediction by identifying the scaling trend of primary parameters and incorporating important correlations among them.The target V
_th
can be achieved by different combinations of channel doping, halo doping and the control of SCE for various design needs. Gate tunneling leakage and HK/MG have been implemented in this predictive model. With solid calibration at 65nm and 45nm nodes, the predictive methodology is applicable to 32nm node and beyond for advanced design research.