A Dy2O3-capped HfO2 Dielectric and TaCx-based Metals Enabling Low-Vt Single-Metal-Single-Dielectric Gate Stack

We show for the first time that conduction and valence band-edge effective work functions (WF) are achieved simultaneously by one single Dy
₂
O
₃
capping layer on HfO
₂
for both nMOS and pMOS with TaC
_x
-based metals. Low V
_t
's (0.23 and -0.36 V) are obtained without degrading the EOT-J
_G
scalability and hole mobility. A model based on competing intermixes of cap/host dielectric and cap/metal is proposed to explain the positive WF shift with TaC
_x
N
_y
and the negative shift with TaC
_x
as compared to the uncapped HfO
₂
reference. Finally, by developing a novel nitridation process to modify TaC
_x
into TaC
_x
N
_y
, this work shows that single-metal-single-dielectric gate stacks are feasible, allowing cost-effective low-V
_t
CMOS integration.