Sleep transistor sizing in power gating designs

Power Gating is effective for reducing leakage power. Previously, a Distributed Sleep Transistor Network (DSTN) was proposed to reduce the sleep transistor area by connecting all the virtual ground lines together to minimize the Maximum Instantaneous Current (MIC) through sleep transistors. In this paper, we propose methodologies for determining the size of sleep transistors of the DSTN structure considering charge-balancing effect. We also introduce a new relationship among MIC, IR drops and sleep transistor networks from a temporal viewpoint and improve the sizing results. Our methods achieve significant better results than previous works.