A 57mW 10-bit 80-MS/s pipeline ADC adopting improved power optimization approach

An improved power optimization algorithm is presented to guide power-driven design of pipeline ADC in this paper. Five options constitute overall procedure including stage resolution distribution, capacitor scaling, stage current control, stage circuit adoption and the final validation. Using the optimization approach, a 0.18-mum 10-bit 80-MS/s CMOS prototype achieves 58.1dB SNARED, 60.14 dB SFDR under 40 MHz input signal, its DNL and INL within +0.69/-0.6 and +0.75/-1.05 LSB respectively. The chip consumes 57mW at 1.8-V power supply and occupies 0.567 mm
²
.