A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR

A 16-channel time-interleaved track and hold is presented. Three techniques are introduced enabling a high bandwidth and linearity and good timing alignment. Integrated ADCs are used to evaluate the performance of the T/H. Single channel performance is 43 dB SNDR at an input frequency of 4 GHz. Multi-channel performance is 48 dB SNDR at 1.35 GS/s with an ERBW of 1 GHz. The power consumption of the T/H including clock-driver and buffers is 74 mW.