A new noise-tolerant dynamic logic circuit design

This work proposes a new noise-tolerant dynamic circuit design. It has been extensively compared to previously published schemes. The new design can achieve a level of noise robustness that is unreachable by the previous proposals. Furthermore, it has minimal delay and energy penalties. Under the same energy-delay product, the proposed design shows a noise-robustness that is increased by up to 116%, in comparison with the existing schemes.