On the FPGA implementation of the Fourier Transform over finite fields GF(2m)

The hardware design and implementation of cyclotomic Fast Fourier Transform (FFT) over finite fields GF(2
^m
) is described. By reformulating the algorithm presented in [8], we introduce a hardware interpretation to design a highly parallel and parameterized architecture of the cyclotomic FFT. Based on four stages and modular structure of last stage, this architecture can operate at different throughput rates. Compared to another implemented algorithm [9] which operates at fc (the system clock frequency), the proposed architecture allows to reach a very high throughput rate which, for 256-point FFT, can get hold of 8.5 fc. An FPGA implementation of the proposed architecture is given where the critical path delay and the hardware complexity are evaluated.