Peripheral Circuitry Impact on LEPROM Threshold Voltage

The fundamental discussion of this paper is to show the influence of peripheral circuits' marginalities, like reading and programming circuitry, on the threshold voltage (V
_th
) distributions of an EEPROM memory array. The initial V
_th
dispersion induced by peripheral circuits' is tracked during cycling/retention test. To understand V
_th
distribution variation within the memory array, simulations are performed using an elementary circuit composed of 128 memory cells. Experimental results are given for an ST-Microelectronics 512 Kbits EEPROM test vehicle.