Breakdown voltage reduction in I-MOS devices

Four-stage strategy has been confirmed to reduce the breakdown voltage of 70-nm impact-ionization MOS (I-MOS) devices. Simulation results showed that it was difficult to reduce the breakdown voltage below -5 V only by scaling down some device parameters such as L
I
, x
j,se
, and t
ox
. Thus, a strained SOI (SSOI) substrate is introduced which has narrow E
G
. Though it consists of pure silicon, when strain is maximized, it is observed that the breakdown voltage reaches -1.25 V, which is much lower than that of GOI substrate.