On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis

In this paper, we propose an approach to generate vectors that invoke high delays. We first identify properties of different types of paths, especially sticky paths, i.e., paths that are functionally sensitizable but not even non-robustly testable. In particular, we show that it is impossible to guarantee detection of sticky path-delay faults. We then identify logic and timing conditions that are necessary to cover a target path and develop a new logic-and-timing implication procedure to exploit these conditions. We incorporate this procedure in a new ATPG that also prioritizes the order in which these conditions are used to generate high quality vectors. We use this ATPG to identify paths that cannot or need not be tested and to generate high quality vectors for all other paths. Experimental results demonstrate that the vectors we generate invoke much higher delays than previously generated vector sets, especially for circuits with many sticky paths.