Widening of FUSI RTP Process Window by Spike Anneal

The Ni-silicide phase formation in FUSI gates was investigated comparing soak and spike anneals for the first RTP step. From both physical analysis on blanket wafers and electrical measurements on nMOS FUSI/HfSiON device it is found that the RTP1 temperature process window (PW) to obtain NiSi or Ni
₃
Si
₂
at the FUSI/dielectric interface is significantly widened for spike anneals (30degC < PW < 50degC) compared to soak anneals (15degC < PW < 25degC). Good overlap between the RTP1 process window for nMOS (NiSi or Ni
₃
Si
₂
at the FUSI/dielectric interface) and the RTP1 process window for pMOS (Ni-rich silicide at the interface) is achieved by the reduction of the poly-Si height for the pMOS gate.