A Configurable Interlock System for RF-Stations at XFEL

The main task of the interlock system is to prevent any damage to the cost expensive components of the RF station. The implementation of the interlock should guarantee a maximum of uninterrupted time of operation which includes the implementation of self diagnostic and repair strategies on module basis. Additional tasks include collection and temporary storage of status information of individual channels; transfer of this information to a higher level control system, but also the enactment of slow control functions. The interlock implementation is based on a 4U 19"-Crate which houses a controller and different slave modules which implement the interface to the components of the RF station. A dedicated, user defined backplane connects the controller to all slave modules. The Controller incorporates a 32-bit RISC NIOS-II processor inside a Cyclone-II FPGA device from ALTERA. The program running on this processor performs all necessary control and monitoring functions to all slave modules in the crate, but not the interlock function itself. The interlock function is implemented as hardwired logic and keeps working, even if the processor stops or the program hangs up. The software performs a system-test on power-up, to test the hardware functionality and the crate configuration. On success, the interlock hardware gets configured for operation and the crate is put into the working state. After initialization higher level applications get loaded. This covers the communication interface to the control system and a diagnostic interface, which is used during installation and trouble shooting. For this purpose, LabVIEW tools are used to present information. In addition, a HTTP server on the interlock controller provides the possibility to change configuration and view actual status information. It also implements tools which allow to reconfigure the whole FPGA design or to upload a new software version via Ethernet.